An integrated circuit typically includes a plastic or ceramic package that encapsulates an electronic circuit, or a plurality of electronic circuits, each of which are formed on a semiconductor substrate. Electrical interconnection between the electronic circuit(s) and the external connections of the package are typically provided by wire bonding, flip-chip soldering, or tape automated bonding (TAB). With increasing complexity and functionality of electronic circuits, such electrical interconnections are commonly required across the surface of the semiconductor die as well as at the periphery of the semiconductor die. Additionally, electrical interconnects between the electronic circuits in a multi-chip module (MCM), where a plurality of electronic circuits have been co-packaged, require electrical interconnections similarly implemented within the entire footprint of the package rather than the periphery.
Consider wire bonding, where such electrical interconnections to any portion of an integrated circuit are easily implemented and function well at low frequencies. Such bond wires can vary in shape (round or flat), width (typically 15 μm to 200 μm), and length (typically 100 μm to 1000 μm). These bond wires represent a high characteristic impedance transmission line segment to a signal propagating within them. However, these wire bonded electrical interconnections become more problematic as data rates and signal frequencies increase, due to inductance, capacitance and resistance parasitics together with variations introduced from the manufacturing processes and equipment. Such parasitics manifest as excessive or variable impedance for the bond wire as signal frequency increases. Such impedance mismatches result in propagating signals having significant attenuations, due to reflection from the controlled impedance environment of the package electrical traces or electrical circuit to the bond wire. Such reflected signals can also cause degraded performance within the electronic circuits and result in distorted signal waveforms and increased noise.
Typically, the prior art solution has been to control or reduce parasitic effects by designing the device to reduce bond wire lengths, thereby reducing the bond wire inductance. Where a bond wire connection is desirable at the device edge, short bond wire lengths are possible and have utility. However, there are device applications where a bond wire is required on the device interior. Surprisingly, despite the plethora of electronic circuits, packaging formats, semiconductor die technologies, operating requirements, and manufacturers worldwide, the prior solutions to addressing the problems of providing high performance electrical interconnections to the electronic circuit have been relatively limited, and suffer significant drawbacks in design of the electronic circuit and package or in their reproducibility and manufacturability, especially for devices with very high electrical interconnect counts. Today packages may range from single transistor packages, such as the 4-pin SOT available from NXP Semiconductors (Package Identity SOT343F), through to multiple chip packages (MCP) such as the 2,116-pin high density BGA available from Renesas Technology (Package Identity PRBG2116FA-A). Accordingly, controlled impedance may be required by one electrical interconnection or all electrical interconnections.
Equally, these requirements for controlled, reproducible electrical interconnections exist throughout the wide range of package formats, pin counts, and signal frequencies present within today's electronic circuits. Examples of such devices range from NXP Semiconductors BFG424F NPN wideband transistor operating with analog input and output ports up to 25 GHz in a 4-pin SOT package, to Analog Devices AD6534 Othello-G Single-chip Direct Conversion GSM/GPRS Transceiver packaged within a 32-lead Lead Frame Chip Scale Package in Very Low Quad format (LFCSP-VQ) with dual analog input ports operating at the standard cellular frequencies of 800 MHz/900 MHz/1800 MHz/1900 MHz and digital output ports providing 64 kb/s digital audio, through to an Intel® Pentium® 4 Extreme processor implemented in 0.13 μm silicon with core operating at 3.5 GHz and packaged in a 775-pin LAND package with 64-bit digital data busses operating at 1066 MHz.
The common solution to the bond wire problem is to reduce the size of the transition by using a flip chip concept or ball grid array (BGA) package, in which contacts of a semiconductor circuit are directly bonded to an adjacent circuit or substrate. Another known solution is filling the transition region with a high dielectric constant material, such as for example an epoxy containing a ceramic. Although these solutions work, they are not applicable in all cases. For example, these solutions are not efficient in the sense that the high frequency signals in the transition might involve only a few of the interconnections in the transition. Therefore, the existing solutions become costly and inefficient to implement when only a few transition interconnections require special treatment for high frequency parasitic effects, or the materials within the semiconductor circuit cannot withstand the temperatures from the solder ball reflow operations in the above flip-chip and BGA solutions.
Techniques to reduce or control parasitic effects in bond wire configurations have included providing a plurality of parallel layers of bond wires, for example Grellman et al [U.S. Pat. No. 4,686,492], such that the inductive reactance of the bond wire is compensated by the capacitive reactance of the parallel bond wires. However, such a technique requires that the bonding pads on each end of the bond wire be capable of supporting three, four or more wire bonds, resulting in very large bond pads and increased semiconductor die footprints and cost. Equally, providing such parallel layers over long distances, with semiconductor die footprints reaching 25 mm square or more, results in fragile interconnects that cannot withstand the environmental requirements of electronic packaging. Finally, a 2,116 pin package with a 4-layer bond wire configuration as depicted by Grellman et al requires 8,464 bond wires to be placed, and 16,928 individual bond landings of the wire bonding tool to the package and semiconductor die, resulting in reduced yields, increased manufacturing times, and increased cost.
An alternative presented by Kwark et al [US Patent Application 2005/0,116,013] involves providing a second bond, using a wider flat bond (commonly referred to as ribbon bonding), beneath the main wire bond. The resulting electrical connection provides a microstrip structure. As with Grellman et al the approach suffers from requiring increased die footprint, typically in dimensionally sensitive areas for high speed interconnections; requires providing additional ground bond pads adjacent to every bonding pad featuring the microstrip structure; and doubles the number of mechanical bonding operations.
Each of the solutions taught by Kwark and Grellman solve the issue of controlling the impedance individually for each bond wire. In contrast, Wyland [U.S. Pat. No. 7,217,997] teaches to provide a wide electrical plane above the wire bonds, with a dielectric spacer between to prevent an electrical short circuit between the signal wire bond and the wide electrical plane. As taught by Wyland the impedance of a wire bond can be reduced from the approximately 125Ω of a discrete wire bond to a typical 50Ω of an analog signal input/output by providing the wide electrical plane approximately 32 μm from the bond wire. Advantageously the approach taught by Wyland provides a single feature, the wide electrical plane, allowing a plurality of wire bonds to be managed simultaneously.
However, Wyland teaches that the wide electrical plane above the wire bonds can reduce the impedance to 50Ω but not significantly lower, due to the already small gap of 32 μm resulting in both tight tolerances and substantial variations in impedance for small variations or deviations in this gap. Further, the provision of such impedance controlled structures is best suited to designs wherein the bond wires are connected solely to the periphery of the semiconductor circuit and bonded directly to the package electrical traces. It would also be evident that the structure does not allow the semiconductor circuit designer latitude to provide bond wires close together but of different impedance, such as may be required in providing multiple outputs of different impedance such as 50Ω and 75Ω or the interconnection of very low impedance electronic circuits, such as amplifier gain stages of a few ohms within an MCM in close proximity to a 50Ω output port.
Accordingly it would be beneficial to provide a method of providing controlled impedance for bond wires irrespective of their placement within the semiconductor die or package. It would be further beneficial if the method allowed the impedance of different bond wires to be individually established whilst allowing provisioning of a single additional element during manufacturing and assembly. Additional benefit may be further obtained if the additional element was capable of integration with an electrical signal interconnection to provide the bond wires as a single-piece part, in order to reduce the complexity of the packaging process of the semiconductor circuit, MCM, etc. Further, a method allowing the required structures to be pre-manufactured and including the effect of additional dielectric materials present within the finished device, such as encapsulants, would be advantageous.